The resistivity of interconnect materials is the primary determinant of integrated circuit (IC) speed for current and future devices. Patterns are normally generated in these materials by plasma-assisted (subtractive) etching. However, due to the inability to form volatile copper (Cu) etch products during halogen-based plasma etching, damascene technology was introduced to avoid the need for Cu plasma etching. Although damascene technology played an essential role in the initial implementation of Cu metallization, a critical limitation has arisen where the electrical resistivity of Cu increases rapidly as lateral dimensions are reduced below 100 nm, approaching the electron mean free path in Cu (40 nm at 25° C.).